(Santa
Clara, CA) The electronic
circuit, physical layer, is abbreviated PHY.
For the most part, this type of electronic circuit is implemented as a
chip. The purpose is to implement
physical layer functions of the O.S.I. Model.
This is done by connecting a link layer device, to a physical
medium. For example, a M.A.C. or medium
access control, to, an optical fiber or copper cable. When it comes to a PHY device; a physical
coding sublayer (P.C.S.), and, physical medium dependent (P.M.D.) are required. At the same time, and also operating a
physical layer of the O.S.I. Network Model is, the Ethernet PHY. Recently, Marvell Technology Group, Ltd.
announced that, it has arrived at the milestone industry’s first. Specifically, the aforementioned business
revealed that, it has added to its Alaska C Ethernet transceiver family. The latest edition is officially named,
Marvell’s Alaska C 88X9121P. The latter,
is the industry’s first dual 400 GbE physical layer (PHY) transceiver.
The dual 400 Gigabit Ethernet (GbE) PHY
transceiver function, of Marvell’s Alaska C 88X9121P, also comes with the
following. The 88X9121P comes with 100 G
serial input/output (I/O), and, a M.A.C. Security feature. M.A.C. Security, also MACsec, is an 802.1AE
I.E.E.E. security technology solution.
The purpose is to provide secure communications, for all traffic on
Ethernet links. However and returning
to, Ethernet PHY, the aforementioned is also called Ethernet physical
transceiver. The Ethernet physical layer
portion is usually based on the standards; 1000BASE-T, 100BASE-TX and
10BASE-T. In a more technical manner, an
Ethernet PHY is a chip. This chip
successfully implements the hardware, send and receive functions of Ethernet
frames. The purpose is to interface
between the analog domain of the Ethernet’s line modulation, and, the digital
domain of link layer packet signaling. A
network interface card (N.I.C.) can be one chip, or, it can be several
independent chips. Irregardless of
which, an N.I.C. can contain a PHY, M.A.C or other types of functions.
Returning to, Marvell’s Alaska C
88X9121P, the aforementioned technology solution is an integrated circuit
transceiver (I.C.) or chip.
Additionally, it has a serializer/deserializer (SerDes) feature. This feature converts parallel data into
serial data, and, vice versa. The
previously said; is perfectly suited for high density implementations in the
data center, and, the internet cloud. As
previously said, the 88X9121P is the technology industry’s first, dual 400 GbE
physical layer (PHY) transceiver.
Additionally, it comes with 100 GbE serial electrical I/O capabilities. The idea is to lead the next generation, of
secured high density optical infrastructure.
In order to accomplish this effort, three features help to define
Marvell’s Alaska C 88X9121P. The first
feature that defines, is the 100 G serial inputs/outputs enable the doubling of
faceplate bandwidth. The latter, occurs
at the data center network.
Additionally; it reduces the total power consumption, and, cost per
bit. The second feature that defines, is
the 256 bit M.A.C Security encryption.
The latter, ensures a heightened point to point security. Additionally; it provides a compliant Class C
precision time protocol (P.T.P.), time stamping that enables synchronization
and a 112 G P.A.M 4 serializer/deserializer.
The serializer/deserializer is meant for use on high density 400 GbE,
and, 100 GbE deployments. The third
feature that defines is; the 88X9121P is completely compliant with I.E.E.E.
standards for 400 GbE, 100 GbE and 50 GbE.
The latter; actually exceeds the electrical specifications that are
needed, to be able to, interface with Q.S.F.P.-D.D. and O.S.F.P. optical
modules. Bob Wheeler is a Principal
Analyst for Networking at The Linley Group.
Through a press statement, Mr. Wheeler said the following. “We see 100Gbps serial I/O as a foundational
speed and expect it will enable 400GbE port shipments to reach 6.5 million by
2023. Marvell’s new PHY is a milestone
in kickstarting the ramp of 100Gbps-serial-electrical optics and will help
accelerate the deployment of 400GbE in cloud data centers.”
To end, Marvell Technology Group,
Ltd. (NASDAQ: MRVL) did release press
statements. Faraj Aalaei is the
Executive Vice President of the Networking Business Group at Marvell Technology
Group, Ltd. Through a press statement,
Mr. Aalaei said the following. “We see
the introduction of our feature-rich 100G serial I/O based, dual 400GbE PHYs
playing a major role in the next evolutionary phase of the global data center
and cloud sectors. The transition to
100G serial signaling is critical for high-density optical interconnects
required for next-generation switching solutions. Our newest PHY transceivers
will help drive the industry transition to 100G serial I/O-based optics as data
centers and cloud providers look to bring greater computing bandwidth and
efficiency to their customers.” Sandeep
Bharathi is the Senior Vice President of Central Engineering at Marvell
Technology Group, Ltd. Through a press statement,
Mr. Bharathi said the following.
“Marvell has a rich history of innovation in SerDes technology that is
further strengthened by our SoC design and Ethernet expertise. Our newest PHY transceiver device extends
Marvell’s SerDes technology leadership by integrating our state-of-the-art 112G
PAM4 SerDes solution in advanced FinFET process into the industry’s first dual
400GbE MACsec PHY with 100GbE serial I/Os.”
As previously stated, Marvell Technology Group, Ltd. recently announced
that, it has arrived at the milestone industry’s first. Specifically, the aforementioned business
revealed that, it has added to its Alaska C Ethernet transceiver family. The latest edition is officially named,
Marvell’s Alaska C 88X9121P. The latter,
is the industry’s first dual 400 GbE physical layer (PHY) transceiver. Lastly; the 88X9121P comes with 100 G serial
input/output (I/O), and, a M.A.C. Security feature.
###
Written
from Press Release
Registered
Writer with
PR
Newswire Association, LLC
R-Berumen28
03/13/2020
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